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DC poleHodnotaJazyk
dc.contributor.authorVacula, Patrik
dc.contributor.authorHusák, Miroslav
dc.contributor.editorPihera, Josef
dc.contributor.editorSteiner, František
dc.date.accessioned2015-01-19T09:57:31Z
dc.date.available2015-01-19T09:57:31Z
dc.date.issued2014
dc.identifier.citationElectroscope. 2014, č. 3, EDS 2014.cs
dc.identifier.issn1802-4564
dc.identifier.urihttp://147.228.94.30/images/PDF/Rocnik2014/Cislo3_2014/r8c3c7.pdf
dc.identifier.urihttp://hdl.handle.net/11025/11823
dc.format6 s.cs
dc.format.mimetypeapplication/pdf
dc.language.isoenen
dc.publisherZápadočeská univerzita v Plzni, Fakulta elektrotechnickács
dc.relation.ispartofseriesElectroscopecs
dc.rightsCopyright © 2014 Electroscope. All Rights Reserved.en
dc.subjectstruktury MOScs
dc.subjecttranzistory MOScs
dc.titleComparison of Waffle and standard gate pattern base on specific on-resistanceen
dc.typečlánekcs
dc.typearticleen
dc.rights.accessopenAccessen
dc.type.versionpublishedVersionen
dc.description.abstract-translatedThe main goal of this work is to compare the different Waffle MOS structures as function between main dimensions and channel resistance (specific on-resistance). Even if Waffle MOS structure is so general that it is independent on dedicated CMOS process in fact constrains coming from specific CMOS process design rules has main influence on final Waffle MOS shape and final required area. Comparison describing how dimensions of Waffle MOS have influence on channel resistance would be proposed. Due to non-conventional gate geometry of the Waffle MOS transistor compare to the fingers structure, the channel W/L ratio calculation is not trivial and conformal Schwarz-Christoffel Transformation mapping was used.en
dc.subject.translatedMOS structuresen
dc.subject.translatedMOS transistorsen
dc.type.statusPeer-revieweden
Vyskytuje se v kolekcích:Číslo 3 (2014)
Číslo 3 (2014)

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