Full metadata record
DC pole | Hodnota | Jazyk |
---|---|---|
dc.contributor.author | Younes, Dina | |
dc.contributor.author | Šteffan, Pavel | |
dc.contributor.editor | Pihera, Josef | |
dc.contributor.editor | Steiner, František | |
dc.date.accessioned | 2012-11-12T08:57:25Z | |
dc.date.available | 2012-11-12T08:57:25Z | |
dc.date.issued | 2011 | |
dc.identifier.citation | Electroscope. 2011, č. 4, EDS 2011. | cs |
dc.identifier.issn | 1802-4564 | |
dc.identifier.uri | http://147.228.94.30/images/PDF/Rocnik2011/Cislo4_2011/r5c4c8.pdf | |
dc.identifier.uri | http://hdl.handle.net/11025/627 | |
dc.format | 4 s. | cs |
dc.format.mimetype | application/pdf | |
dc.language.iso | en | en |
dc.publisher | Západočeská univerzita v Plzni, Fakulta elektrotechnická | cs |
dc.relation.ispartofseries | Electroscope | cs |
dc.rights | Copyright © 2007-2010 Electroscope. All Rights Reserved. | en |
dc.subject | soustava zbytkových tříd | cs |
dc.subject | modulo 2n+1 sčítačky | cs |
dc.subject | programovatelná hradelná pole | cs |
dc.title | New structures of 2n ± 1 modular adders for FPGAs | en |
dc.type | konferenční příspěvek | cs |
dc.type | conferenceObject | en |
dc.rights.access | openAccess | en |
dc.type.version | publishedVersion | en |
dc.description.abstract-translated | Two new structures of residue number system (RNS) adders for moduli 2n –1, 2n +1 are presented in this paper. The main idea is the utilization of the prefix computation technique in order to make the correction stage enclosed in the addition process instead of leaving it as the last stage of the modular addition. This provides faster and more efficient applications. Both designs allow efficient implementation on field programmable gate array (FPGA). Carry ripple adders (CRA) were utilized in the two structures due to the dedicated carry ripple logic built-in FPGAs. The proposed designs were implemented on Spartan-3 xc3s200-ft256-4 FPGA. A comparison with already published designs was done in terms of time and area consumption and showed significant time savings up to 44.7%. | en |
dc.subject.translated | residue number system | en |
dc.subject.translated | modulo 2n+1 adders | en |
dc.subject.translated | field programmable gate array | en |
dc.type.status | Peer-reviewed | en |
Vyskytuje se v kolekcích: | Číslo 4 - EDS 2011 (2011) Číslo 4 - EDS 2011 (2011) |
Soubory připojené k záznamu:
Soubor | Popis | Velikost | Formát | |
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r5c4c7.pdf | 565,77 kB | Adobe PDF | Zobrazit/otevřít |
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http://hdl.handle.net/11025/627
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