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dc.contributor.authorBurian, Petr
dc.contributor.editorPihera, Josef
dc.contributor.editorSteiner, František
dc.date.accessioned2012-10-04T11:46:18Z-
dc.date.available2012-10-04T11:46:18Z-
dc.date.issued2008
dc.identifier.citationElectroscope. Elektrotechnika a informatika 2008, p. [13-16].en
dc.identifier.isbn978-80-7043-702-5
dc.identifier.issn1802-4564
dc.identifier.urihttp://hdl.handle.net/11025/497
dc.identifier.urihttp://147.228.94.30/images/PDF/Rocnik2008/Dokt08/Elektronika/burian.pdf
dc.format4 s.cs
dc.format.mimetypeapplication/pdf
dc.language.isocscs
dc.publisherZápadočeská univerzita v Plzni, Fakulta elektrotechnickács
dc.relation.ispartofseriesElectroscopecs
dc.rightsCopyright © 2007-2010 Electroscope. All Rights Reserved.en
dc.subjectstandardní genetický algoritmuscs
dc.subjectvyvíjející se obvodycs
dc.titleImplementace genetického algoritmu do obvodu FPGAcs
dc.typekonferenční příspěvekcs
dc.typeconferenceObjecten
dc.rights.accessopenAccessen
dc.type.versionpublishedVersionen
dc.description.abstract-translatedThis paper deals with the implementation of a standard genetic algorithm by an FPGA circuit. It examines the various features of this algorithm. The main goal of this work is building of an evolvable combinational circuit. Demands imposed on an FPGA circuit are researched as well.en
dc.subject.translatedstandard genetic algorithmen
dc.subject.translatedevolvable hardwareen
dc.type.statusPeer-revieweden
Appears in Collections:2008
Články / Articles (RICE)
Elektrotechnika a informatika 2008 (2008)
2008

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