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DC poleHodnotaJazyk
dc.contributor.authorBarri, Dalibor
dc.contributor.authorVacula, Patrik
dc.contributor.authorKotě, Vlastimil
dc.contributor.authorVacula, Miloš
dc.contributor.authorJakovenko, Jiří
dc.contributor.authorVoves, Jan
dc.contributor.editorPinker, Jiří
dc.date.accessioned2022-11-03T14:17:34Z
dc.date.available2022-11-03T14:17:34Z
dc.date.issued2022
dc.identifier.citation2022 International Conference on Applied Electronics: Pilsen, 6th – 7th September 2022, Czech Republic, p. 33-38.en
dc.identifier.isbn978-1-6654-9482-3
dc.identifier.urihttp://hdl.handle.net/11025/49846
dc.format6 s.cs
dc.format.mimetypeapplication/pdf
dc.language.isoenen
dc.publisherFakulta elektrotechnická ZČUcs
dc.rights© IEEEen
dc.subjecttechnologie BCDcs
dc.subjecttranzistory MOScs
dc.subjectefektivní prahové napětícs
dc.subjectobdélníkové rozvrženícs
dc.subjectdiamantový tvarcs
dc.titlePrecise Model of the Effective Threshold Voltage Changes in the DLS MOSFETs for Different Gate Angles Compared with Measured Dataen
dc.typekonferenční příspěvekcs
dc.typeconferenceObjecten
dc.rights.accessopenAccessen
dc.type.versionpublishedVersionen
dc.description.abstract-translatedThis paper presents an interesting phenomenon related to the effective threshold voltage changes (δV th,eff ) in the diamond layout shape MOS transistors (DLS MOSFETs). Besides it, its analytical expression is presented here for the first time. The analytical approximative expression has been defined based on the results of the 3-D TCAD simulations for the different effective aspect ratio (W/L) eff and different angle α of DLS MOSFET. The effective aspect ratio has been set to 2.0, 1.5, 1.0, 0.5 with the angle α varied from 180° to 80° with the step 20°. Furthermore, for purpose to verify the 3-D TCAD simulation results and measurement results, 1 124 samples were fabricated, which were proportionally divided into rectangle layout shape (RLS) MOSFETs and DLS MOSFETs with the angles α equal to 120°, 100°, and 80°. All the samples have been fabricated in the 160 nm BCD technology process. The mentioned phenomenon described by the proposed expression fits the measured data with a very high level of accuracy equal to 99.995 %. Thus, the presented analytical expression proves its quality. Thanks to the high level of the expression quality, the given expression is recommended to use for the analog designs with high-level precision requests and DLS MOSFET components.en
dc.subject.translatedBCD Technologyen
dc.subject.translatedDiamond Layout Shape MOS Transistoren
dc.subject.translatedeffective threshold voltageen
dc.subject.translatedRectangular Layout Shape MOS Transistoren
dc.type.statusPeer-revieweden
Vyskytuje se v kolekcích:Applied Electronics 2022
Applied Electronics 2022



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