| Title: | High Performance, Low Power Architectureof 5-stage FIR Filter using ModifiedMontgomery Multiplier |
| Authors: | Thanmai, T. Ravindra, JVR |
| Citation: | 2020 International Conference on Applied Electronics: Pilsen, 8th – 9h September 2020, Czech Republic. |
| Issue Date: | 2020 |
| Publisher: | Západočeská univerzita v Plzni |
| Document type: | conferenceObject konferenční příspěvek |
| URI: | http://hdl.handle.net/11025/39929 |
| ISBN: | 978-80-261-0891-7 (Print) 978-80-261-0892-4 (Online) |
| ISSN: | 1803-7232 (Print) 1805-9597 (Online) |
| Keywords: | kryptografie;Montgomeryho multiplikátor;kompresor;FIR filtr |
| Keywords in different language: | cryptography;Montgomery Multiplier;compressor;FIR Filter |
| Abstract in different language: | In the field of VLSI, enhancement is promi-nent. Arithmetic circuits are one of the influential sectorsin today’s end products of electronics, where multipliersare one of the deciding factors of efficiency. Multiplierplays an important role in different applications suchas digital signal processing in which it acts as a keyhardware block. As time rolls down, the technologyexposed the ways for the initiation of many hardwareand software implementations of the faster multipliers.One among them is the Montgomery multiplier. Thefundamental operation in the Montgomery multiplier isthe modular multiplication. It is mainly used in FIRfilters, which in-turn has numerous applications suchas speech analysis, multi-rate signal processing, adaptivefilters, and averaging filters. With the usage of proposedcompressor in the conventional design of the multiplier,the number of transistor count has been declined by asignificant amount and made the design into an optimalarea design. This paper presents a modified Montgomerymultiplier design and its implementation in the5thorderFIR filter. The entire design simulation is carried outusing CMOS and PTL logic in 45 nm technology. Thereis an escalation in the result outcomes, and the multiplierhas an area efficiency of 65% and a power reduction ofabout 68% in comparison with conventional design. |
| Rights: | © Západočeská univerzita v Plzni |
| Appears in Collections: | Applied Electronics 2020 Applied Electronics 2020 |
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| File | Description | Size | Format | |
|---|---|---|---|---|
| 09232853.pdf | Plný text | 2,76 MB | Adobe PDF | View/Open |
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