Title:	LHC clock conditioning circuit for AFP trigger module
Authors:	Georgiev, Vjačeslav Zich, Jan
Citation:	GEORGIEV, V., ZICH, J. LHC clock conditioning circuit for AFP trigger module. In: International Conference on Applied Electronics (AE 2020) : /proceedings/. Pilsen: University of West Bohemia, 2020. s. 187-190. ISBN 978-80-261-0891-7 , ISSN 1803-7232.
Issue Date:	2020
Publisher:	University of West Bohemia
Document type:	konferenční příspěvek conferenceObject
URI:	2-s2.0-85096361046 http://hdl.handle.net/11025/42396
ISBN:	978-80-261-0891-7
ISSN:	1803-7232
Keywords in different language:	CERN, delay lines;high energy physics;LHC;particle accelerator;clock conditioning, physical instrumentation;synchronization;rad-hard
Abstract in different language:	The timing and synchronisation of the detectors in particle physics play the key role due to the high event rates at particle accelerators. The trigger module in ATLAS Forward Physics project selects the events from time of flight d etector belonging to the proton bunch. As the time position of the proton bunch is the same within each Large Hadron Collider period, from the clock conditioning circuit (CCC) can be derived the qualification signal for the trigger module input signals. The further processing of these events in trigger module is allowed by the CCC qualification. High speed delay line integrated circuits together with the logic gates and FPGA based controller were used for the realization of the CCC. This paper describes the design, construction and test procedure of the CCC.
Rights:	© University of West Bohemia in Pilsen
Appears in Collections:	Konferenční příspěvky / Conference papers (RICE) Konferenční příspěvky / Conference Papers (KEI) OBD

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