Full metadata record
DC poleHodnotaJazyk
dc.contributor.authorDeka, Debarshi
dc.contributor.authorKumar, Navaneeth
dc.contributor.authorPal, Dipankar
dc.contributor.editorPinker, Jiří
dc.date.accessioned2021-10-27T09:57:01Z
dc.date.available2021-10-27T09:57:01Z
dc.date.issued2021
dc.identifier.citation2021 International Conference on Applied Electronics: Pilsen, 7th – 8th September 2021, Czech Republic, p. 39-42.en
dc.identifier.isbn978–80–261–0972–3 (Print)
dc.identifier.isbn978–80–261–0973–0 (Online)
dc.identifier.issn1803–7232 (Print)
dc.identifier.issn1805–9597 (Online)
dc.identifier.urihttp://hdl.handle.net/11025/45562
dc.format4 s.cs
dc.format.mimetypeapplication/pdf
dc.language.isoenen
dc.publisherUniversity of West Bohemiaen
dc.rights© University of West Bohemia, 2021en
dc.subjectplovoucí desetinná čárkacs
dc.subjectalgoritmus vzdálené a blízké datové cestycs
dc.subjectkadence rod a innovuscs
dc.subjectKogge–Stone sčítačcs
dc.subjectbarrel shiftercs
dc.subjecthlavní prediktorcs
dc.subjectsčítačkacs
dc.subjectnormalizovaná, denormalizovaná a smíšená číslacs
dc.subjectASICcs
dc.titleDesign of an ASIC-Based High Speed 32-bit Floating Point Adderen
dc.typekonferenční příspěvekcs
dc.typeconferenceObjecten
dc.rights.accessopenAccessen
dc.type.versionpublishedVersionen
dc.description.abstract-translatedAdvancements in machine-learning algorithms made it necessary to explore fast algorithms for Floating Point operations, addition being most commonly used complex operation involving significant delay and power-consumption. Applications include high-performance computer vision, imaging and deep-learning functions accelerated using dedicated hardware accelerators. This paper proposes a 32-bit Floating Point Adder based on the ‘Far-and-Close-Data-Path Algorithm’ with added optimizations to give a better implementation in terms of overall minimum latency and improved accuracy for certain input cases. The designs have been coded in Verilog, synthesized in Cadence Genus and physically verified with Cadence Innovus in GDSII under ASIC platformen
dc.subject.translatedASICen
dc.subject.translatedFloating Point Adderen
dc.subject.translatedFar and Close Data Path Algorithmen
dc.subject.translatedcadence genus and innovusen
dc.subject.translatedKogge-Stone adderen
dc.subject.translatedBarrel Shifteren
dc.subject.translatedLeading One Predictoren
dc.subject.translatedcompound adderen
dc.subject.translatednormalized, denormalized and mixed numbersen
dc.type.statusPeer-revieweden
Vyskytuje se v kolekcích:Applied Electronics 2021
Applied Electronics 2021

Soubory připojené k záznamu:
Soubor Popis VelikostFormát 
Design_of_an_ASIC-Based_High_Speed_32-bit_Floating_Point_Adder.pdfPlný text1,04 MBAdobe PDFZobrazit/otevřít
Zobrazit minimální záznam Zobrazit statistiky


Použijte tento identifikátor k citaci nebo jako odkaz na tento záznam: http://hdl.handle.net/11025/45562

Všechny záznamy v DSpace jsou chráněny autorskými právy, všechna práva vyhrazena.

hledání
navigace
  1. DSpace at University of West Bohemia
  2. Publikace ZČU / UWB Publications
  3. Sborníky ZČU / UWB Proceedings
  4. Applied Electronics
  5. Applied Electronics 2021