Title:	Design of an ASIC-Based High Speed 32-bit Floating Point Adder
Authors:	Deka, Debarshi Kumar, Navaneeth Pal, Dipankar
Citation:	2021 International Conference on Applied Electronics: Pilsen, 7th – 8th September 2021, Czech Republic, p. 39-42.
Issue Date:	2021
Publisher:	University of West Bohemia
Document type:	konferenční příspěvek conferenceObject
URI:	http://hdl.handle.net/11025/45562
ISBN:	978–80–261–0972–3 (Print) 978–80–261–0973–0 (Online)
ISSN:	1803–7232 (Print) 1805–9597 (Online)
Keywords:	plovoucí desetinná čárka;algoritmus vzdálené a blízké datové cesty;kadence rod a innovus;Kogge–Stone sčítač;barrel shifter;hlavní prediktor;sčítačka;normalizovaná, denormalizovaná a smíšená čísla;ASIC
Keywords in different language:	ASIC;Floating Point Adder;Far and Close Data Path Algorithm;cadence genus and innovus;Kogge-Stone adder;Barrel Shifter;Leading One Predictor;compound adder;normalized, denormalized and mixed numbers
Abstract in different language:	Advancements in machine-learning algorithms made it necessary to explore fast algorithms for Floating Point operations, addition being most commonly used complex operation involving significant delay and power-consumption. Applications include high-performance computer vision, imaging and deep-learning functions accelerated using dedicated hardware accelerators. This paper proposes a 32-bit Floating Point Adder based on the ‘Far-and-Close-Data-Path Algorithm’ with added optimizations to give a better implementation in terms of overall minimum latency and improved accuracy for certain input cases. The designs have been coded in Verilog, synthesized in Cadence Genus and physically verified with Cadence Innovus in GDSII under ASIC platform
Rights:	© University of West Bohemia, 2021
Appears in Collections:	Applied Electronics 2021 Applied Electronics 2021

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